This invention relates generally to fault tolerant devices and, more particularly, to triple redundant fault-tolerant integrated circuits.
Integrated circuits (IC's) used in computers and other electronic systems aboard space vehicles are susceptible to a phenomenon known as Single Event Upset, or SEU. Single Event Upset occurs when radiation passing through an integrated circuit deposits stray charges in the device, causing one of its registers to be disrupted.
Several fault protection techniques can be utilized to reduce the number of SEU's that occur in the integrated circuits used aboard space vehicles. One technique is to increase the size of the registers, as a larger register requires a greater amount of stray charge for an SEU to occur. However, the resistance to Single Event Upset only increases linearly with area. Therefore, a rather large tenfold increase in the area of a register only improves the resistance to upset by ten times.
Another technique for reducing Single Event Upset is to encode the contents of the registers with some type of error correction. However, conventional error correction techniques require a "scrubbing" process, in which the data is frequently read out from a register, corrected, re-encoded and restored in the register. This scrub cycle interrupts the normal use of the register and, if multiple errors occur between scrub cycles, the scrubbing process will not be successful in correcting the errors.
The disadvantages associated with these conventional fault protection techniques has made it apparent that a new technique for protecting IC registers from Single Event Upset is needed. The new technique should be self correcting and should not require a large increase in circuit area or require error correction and its attendant scrubbing process. The present invention is directed to these ends.